(a) Field of the invention
The present invention is related to a static induction transistor logic (SITL) circuit.
(b) Description of the prior art
The SITL circuit is a unique modification of the conventional IIL circuit and is comprised of a driver static induction transistor and an injector bipolar transistor. This SITL circuit has been employed in those semiconductor devices such as disclosed in Japanese patent application No. 50-146588 (corresponding U.S. patent application Ser. No. 748,292/1976 by Jun-ichi NISHIZAWA) and in Japanese patent application No. 51-92467 (corresponding U.S. patent application Ser. No. 819343/1977 by Jun-ichi NISHIZAWA et al) for instance.
In FIG. 1 is illustrated a basic example of the SITL circuit, in which Q.sub.i is the injector bipolar transistor of pnp type and Q.sub.d is the driver static induction transistor of n-channel type. The collector C of the injector transistor Q.sub.i is connected to the gate G of the driver transistor Q.sub.d. The base B of the injector transistor Q.sub.i is connected to the source S of the driver transistor Q.sub.d. For usual operation, a constant voltage V.sub.EE is applied to the emitter E of the injector transistor Q.sub.i, thus causing a substantially constant current to flow through the injector transistor Q.sub.i. In case the input terminal, i.e. the gate G of the driver transistor Q.sub.d, is opened, the gate capacitance of the driver transistor is charged with a current supplied by the injector transistor up to a high potential, so that the driver transistor turns to be conductive with its drains D.sub.1 and D.sub.2 being substantially grounded. On the other hand, when the gate G of the driver transistor is shorted to the source S, the current supplied by the injector transistor is allowed to flow through the shorting path, and the gate capacitance of the driver transistor is discharged, so that the driver transistor turns to be non-conductive, thus the drains D.sub.1 and D.sub.2 being rendered to a high impedance condition, and a high-level voltage.
As such, the manner of operation of the SITL circuit can be said to be similar to that of the conventional IIL circuit, but the SITL circuit has many advantages over the conventional IIL circuit, as will be described below.
First, a static induction transistor, basically, is a majority carrier control device, and therefore the minority carrier storage effect in the driver static induction transistor is greatly reduced as compared with that noticed in the driver bipolar transistor of the conventional IIL device. Consequently, the SITL device can make switching operations at a greatly increased speed.
Second, the static induction transistor, basically, is a voltage-controlled device, so that only a small amount of power is required for driving the driver static induction transistor and that the driver transistor can be easily coupled to an external circuit. Also, the power loss in the driver static induction transistor itself is small. Accordingly, the SITL circuit will allow a high density integration.
Third, a static induction transistor has a large transconductance and can provide a large number of fan-outs. As a result, the SITL circuit can consititute any logic circuit as required, in a simplified arrangement.
Fourth, the SITL circuit is easy to be formed as an integrated semiconductor circuit as shown in FIGS. 2 and 3.
FIG. 2 shows a top plan view of an example of an integrated SITL circuit in which is incorporated two units of SITL circuits shown in FIG. 1. FIG. 3 illustrates a vertical section taken along the line III--III of FIG. 2. Each unit of the SITL circuit includes a semiconductor wafer 10 consisting of a heavily doped n.sup.+ type substrate 13 and a lightly doped n.sup.- type layer 14. In some case n.sup.+ layer 13 is a buried layer in a p type substrate. In the semiconductor layer 14 are provided a heavily doped p.sup.+ type region 11. and a heavily doped p.sup.+ type region 12 of a mesh-like shape. In the upper portion of the layer 14, those portions surrounded by the regions 12, there are provided heavily doped n.sup.+ type regions 15 and 16. Regions 11, 12 and a portion of the layer 14 which is sandwiched between these regions 11 and 12 jointly constitute a lateral bipolar transistor serving as an injector transistor Q.sub.i as shown in FIG. 1. In further detail, the region 11 functions as an emitter; the region 12 serves as a collector; and the sandwiched portion of the layer 14 serves as a base. On the other hand, regions 12, 13, 14, 15 and 16 form, jointly therewith, a static induction transistor serving as a driver transistor Q.sub.d as shown in FIG. 1. More particularly, the substrate 13 functions as a source; the region 12, functions as a gate; and the regions 15 and 16 serve as drains. The current channels of the static induction transistor are defined to be those portions of the layer 14 which are surrounded by the region 12. There are provided, on the corresponding locations, drain electrodes D.sub.1 and D.sub.2, a gate/collector electrode G/C, an emitter electrode E, and a source/base electrode S/B. A passivation film layer 17, such as a silicon dioxide film layer, is formed on the exposed upper surface of the semiconductor wafer 10.
As will be easily understood from FIGS. 2 and 3, the SITL circuit can be manufactured as an integrated semiconductor circuit by relying on a simple processing technique wherein the impurity diffusion step is conducted only two times and four masks are required at most, for instance.
With such a simple structure as well as such a simple processing, there has been obtained an integrated SITL circuit whose power delay product for low current operation is decreased to as low as 0.002 pJ or less. Furthermore, a specimen of such integrated SITL circuit exhibiting a minimized delay time of 13.8 nano-seconds or less in an operation with a power dissipation of 230 micro-watts has been materialized according to the structure of FIGS. 2 and 3. In this specimen, the semiconductor layer 14 has an impurity concentration of about 10.sup.14 atoms/cm.sup.3 and a thickness of about 6 micro-meters, the gate region 12 has an impurity concentration of about 10.sup.17 atoms/cm.sup.3 or more, and a thickness of about 2 micro-meters, and the gate mask distance is set to be about 6 micro-meters. The above-mentioned delay time of the SITL circuit contains several factors such as a delay for charging up the gate capacitance of the driver transistor, a delay for carrier transit across the source and the drain of the driver transistor, a carrier storage effect due to unnecessary minority carriers injected from the gate into a high resistivity region around the gate other than the current channel of the driver transistor, a carrier storage effect due to excessive minority carriers injected from the gate into the current channel, and like factors. The former three factors may be reduced drastically, by minimizing the thickness of the high resistivity layer 14 (see FIG. 3) to thereby bring the gate 12 into a substantial contact with the low resistivity layer 13, and thereby to reduce the effective distance between the source and the drains, and by minimizing the effective area of the gate 12, for instance. The provision of an insulator region at the outer boundary of the gate of the driver transistor may be effective for preventing the occurrence of an unnecessary carrier injection at the boundary. The last factor may also be somewhat reduced by a decrease in the gate area. In this manner, there has been obtained, in fact, a specimen of the SITL device whose delay time is reduced to as small as 4 nano-seconds or less.
The afore-mentioned excellent operating characteristic of the SITL circuit can never be attained by the use of a conventional IIL circuit, particularly by the use of the conventional IIL circuit designed to provide many fan-outs. Some known modified IIL circuit comprised of only bipolar transistors, such as the known VIL (Vertical Injection Logic) circuit and SSL (Self-Aligned Super Injection Logic) circuit, might be seen as being somewhat comparable to the SITL circuit only in the delay time characteristic (representative minimum delay time is 8 nano-seconds), but their power.multidot.delay product is roughly thirty times or more as large as that of the SITL device. Moreover, these known modified IIL circuits are extremely hard to be formed into an integrated semiconductor circuit having a simplified structure.
The SITL circuit of the prior art, though it has many excellent features as described above, still leaves a problem to be improved. This problem is represented by the minority carrier storage effect which is developed in the driver transistor. This carrier storage effect is caused by an excessively large amount of minority carriers injected into the current channel from the gate of the driver transistor when the driver transistor is in the conducting state. Namely, the current which is supplied by the injector transistor, after having charged the gate capacitance of the driver transistor up to a required potential, will continue to flow, to charge the gate capacitance up to an excessively high potential, because the injector current is usually kept almost constant. As a result, the gate junction of the driver transistor is deeply forwardbiased, so that an excessively large amount of carriers are injected, thus bringing about the above-mentioned carrier storage effect in the driver transistor. Since a static induction transistor employed for the driver transistor, basically, is a majority carrier control device, the degree of the carrier storage effect which develops in the driver transistor is very low as compared with that in the driver bipolar transistor of the conventional IIL circuit. However, the carrier storage effect constitutes a great obstruction in attaining a further increase in the operating speed of the SITL circuit of the prior art.
To eliminate such carrier storage effect in the driver transistor of the SITL circuit, it has been found very effective to use a modification of the circuit such that the injector bipolar transistor is replaced by a static induction transistor. This modified SITL circuit has been proposed in Japanese Patent Application No. 52-4633 (corresponding U.S. patent application No. 867298/1978 by Jun-ichi NISHIZAWA), and in Japanese Patent Application No. 52-15879, laid open Sept. 2, 1978 with publication No. 53,100783, wherein the inventor is Jun-ichi NISHIZAWA. Suppose, here, that a device which is employed as an injector transistor has such ideal drain voltage V.sub.ds versus drain current I.sub.d characteristic as shown by the solid line in FIG. 4, in which after the gate potential of the driver transistor has exceeded a certain potential V.sub.go necessary to render the driver transistor conductive, the injector current I.sub.d becomes suppressed to a desirable minimized value. In case an injector transistor has such characteristic as stated just above, the unnecessary excessive minority carrier injection in the driver transistor can be suppressed, and thus the carrier storage effect is greatly reduced. In addition, if the injector transistor is able to supply a sufficiently large amount of current to quickly charge the gate capacitance of the driver transistor up to said certain potential V.sub.go, a sufficiently high speed turning-on operation could be performed by the drive transistor. It should be noted, however, that an actual static induction transistor has such a drain voltage versus drain current characteristic as shown by the dash-and-dot line in FIG. 4. Namely, as the gate capacitance of the driver transistor is being charged up with the injector drain current and as, thus, the gate potential of the driver transistor together with the drain potential of the injector transistor is being pulled up, the drain current of the injector transistor will tend to gradually decrease because of its decreasing drain voltage. For this reason, practically speaking, it is impossible to accomplish at the same time both the elimination of the excessive minority carrier injection and the quick charging-up of the gate capacitance of the driver transistor, in accordance with such arrangement of the SITL circuit wherein the injector bipolar transistor is replaced by a static induction transistor.